Latched comparators are employed in ADC applications to compare an input voltage signal to a reference voltage signal. Such comparators typically possess large offsets usually as a result of a combination of threshold voltage mismatch that arises from the use of small transistor sizes to meet operating speed requirements and the on and off switching of various transistors. These offsets can limit the minimum difference between the input data signal and the reference signal that the comparator can detect, thereby limiting the accuracy of the ADC. Existing offset calibration approaches require a dedicated calibration phase when the comparator goes offline and cannot be used for data conversion operations.
Many ADCs use dynamic preamplifiers in their latched comparators because they do not consume static power. Comparators that employ dynamic preamplifiers function generally operate on the principle that a difference in input voltages causes a difference in charging/discharging currents when the dynamic preamplifier is switched on. The difference in these currents can lead to unequal charging and discharging times at cross-coupled nodes whereby one node pulls high with respect to a higher power supply and the other pulls low with respect to a lower power supply, thereby enabling the comparator to make a decision.
If the comparator has an offset, then a non-zero differential input voltage can still lead to unequal currents being produced when the latch is enabled. As will be explained in greater detail herein, if an external current is introduced into the comparator to counter the effect of this residual current, the effect of the input-referred offset can be mitigated.